The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a device under test (DUT) such as a semiconductor device 10 receives an input signal 12 from a test apparatus (such as test module 14) to determine whether an appropriate output signal 16 is generated based on the input signal 12. For example, the test module 14 may include a pattern generator module 18 that provides the input signal 12. The semiconductor device 10 generates the output signal 16 based on the input signal 12.
The test module 14 samples the output signal 16 to determine whether the semiconductor device 10 generated the proper output signal 16. For example, the test module 14 may include a sampling module 20 that receives and samples the output signal 16. The test module 14 stores the samples (i.e. measurement results) of the output signal 16 in, for example, a memory 22. The test module 14 determines a status (e.g. a pass or fail status) of the semiconductor device 10 based on the measurement results of the output signal 16 that are stored in the memory 22. For example, the test module 14 may include a comparison module 24. The comparison module 24 compares the measurement results to stored values that are indicative of a proper (i.e. expected) output signal in view of the input signal 12.
In this manner, the test module 14 determines whether the device under test (i.e. the semiconductor device 10) operates according to a predetermined specification. For example, a test apparatus for testing a synchronous DRAM may input a predetermined input signal to the synchronous DRAM, capture an output signal of the synchronous DRAM corresponding to the input signal, and compare the output signal with an expected value.
Referring now to FIG. 2, the semiconductor device 10 may be connected to the test module 14 via a socket on a test head 30. The semiconductor device 10 receives the input signal 12 from the test module 14 via the test head 30. Similarly, the test module 14 receives the output signal 16 from the semiconductor device 10 via the test head 30.
The test module 14 may be designed to test multiple semiconductor devices simultaneously, which increases the size of the test module 14. As the size of the test module 14 increases, signal lines (i.e. signal lines for the input signal 12 and the output signal 16) between the test module 14 and the semiconductor device 10 (and/or the test head 30) increase in length. As the signal line length increases, validity of the test results may decrease. For example, the device under test may be tested under conditions that differ from the actual operation of the device (e.g. as a result of signal line attenuation).